1. Field
This disclosure relates generally to data processing systems, and more specifically, to a data processing system having compensation for injection locking.
2. Related Art
A data processing system may require multiple clock signals for certain applications. Typically, a number of phase-locked loops (PLLs) may be used to generate the clock signals. PLLs are designed to keep the output clock signal in phase with the phase of a reference clock signal. When these PLLs's oscillators are operating at the same frequency or harmonically related frequencies, the oscillators can “injection lock.” Injection locking may pull the PLL output clock signals to not operate in a phase-aligned manner with their respective reference clock signals. This conflict between the inherent operation of the PLLs and injection locking can result in the PLLs generating clock signals with an unacceptable level of jitter.
Typically, this conflict has been resolved by isolating the PLLs to reduce the coupling between the PLLs to an insignificant level. However, isolating the PLLs is no longer an effective solution due to two factors. First, systems utilizing PLLs are increasingly operating at high frequencies, which can result in a higher sensitivity to jitter. Second, the distance between the PLLs is reducing making isolation ineffective.
Accordingly, there is a need for an apparatus and method to compensate for injection locking.